Integrated circuits are what power many of today's consumer electronics, for instance, cellphones, video cameras, portable music players, computers, etc. As customer demand improves integrated circuit performance, faster, more reliable, and higher-density circuits, need to be produced at a lower cost. Packaging goals of the future for these integrated circuits will be met by increasing the density of chips while reducing the number of internal electrical interconnections. Packaging with fewer interconnects can potentially shorten the circuit length, decreases potential failure points, reduce circuit resistance, and reduce inter-line capacitance or cross-talk. Various techniques, such as, flip chip, gall grid array (BGA), chip on board (COB), and multi-chip modules (MCM), have been developed to meet the continued demands for improving integrated circuit system performance.
For even higher density applications, package assemblies including stacked die configurations have been employed. Unfortunately, many of these applications still suffer from bulky configurations, substrate warpage, electrical shorting, alignment difficulties, delamination, and chip floating problems due to low viscosity adhesives.
Thus, a need still remains for a stacked device integrated circuit package system, which, reduces fabrication complexities and provides a low cost alternative to previous methodologies. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.